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Imec, KULeuven and AIST report new process that paves the way toward increased mobility of beyond 10nm MOS devices




17/9/2013

Tensile-strained GeSn MOSFET devices on Si developed using solid phase epitaxy

Leuven (Belgium) and Tsukuba (Japan) September 17, 2013 – KULeuven, imec and AIST have developed a solid phase epitaxy process to integrate GermaniumTin (GeSn) metal-oxide semiconductor field-effect transistor (MOSFET) devices on silicon. For the first time, operation of depletion-mode junctionless GeSn pMOSFET on silicon was demonstrated, an important step toward achieving tensile strain in MOSFET devices, and increasing their mobility.

To improve performance in next-generation scaled complementary metal-oxide semiconductor (CMOS) devices, researchers are exploring the integration of novel materials with superior electron mobility. This includes GeSn, a promising semiconductor candidate as channel material, due to its superior physical properties. GeSn enables increased switching speed of MOSFET devices and can be used in fast optical communication. While most prototype GeSn channel MOSFETs are fabricated on Ge substrates, silicon integration is preferred for CMOS compatibility.

However, epitaxial growth of GeSn on silicon substrates poses several challenges, including limited solubility of Sn in Ge (0.5%), its compositional fluctuations, Sn segregation, and large lattice mismatch (>4%). Therefore, it is critical to suppress these effects to obtain high performance devices with GeSn layers.

Researchers from KULeuven, imec and AIST developed a solid phase epitaxy process, achieving ultrathin (~10nm) single-crystalline GeSn layers on silicon substrates showing tensile strain, attractive for strain engineering of Ge channels. Furthermore, it reduces the difference between the direct and indirect band transition, resulting in acquisition of a direct band gap group IV material. Lastly, due to its non-equilibrium deposition conditions, the new method enables the development of GeSn with high Sn concentrations .

By decreasing the channel thickness with reactive ion etching (RIE) from ~30 to ~10 nm, the researchers improved the on/off ratio by more than one order of magnitude. Additionally, hole depletion in the ultrathin (~10 nm) GeSn layers on silicon resulted in good transfer characteristics with an on/off ratio of 84. In the future, research will focus on optimizing the GeSn MOSFET on silicon devices to further increase the channel mobility.

More details on these results will be presented at the Solid State Devices and Materials (SSDM) conference in Fukuoka, Japan on September 25, and will be published in Applied Physics Express 2013.


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TEM image of NiGeSn metal S/D MOSFET. TEM is observed along [11-2], the channel direction is [-110] and the surface orientation is (111)

Caption: TEM image of NiGeSn metal S/D MOSFET. TEM is observed along [11-2], the channel direction is [-110] and the surface orientation is (111)
Click on the picture to download the high-res version.

About imec
Imec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China, India and Japan. Its staff of more than 2,000 people includes more than 650 industrial residents and guest researchers. In 2012, imec's revenue (P&L) totaled 320 million euro. Further information on imec can be found at www.imec.be.
Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a "stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shanghai) Co. Ltd.) and imec India (Imec India Private Limited).

About AIST
The National Institute of Advanced Industrial Science and Technology (AIST), led by President Chubachi, is a public research institution funded by the Japanese government to a large extent. The present AIST is a rather new research organization established in 2001. However, AIST and its predecessor organizations have been contributing to society through continuous advancement in technologies and support to Japanese industries since 1882.
Headquarters of AIST are located in Tsukuba and Tokyo. AIST has over 40 autonomous research units in various innovative research fields, and the units are located at nine research bases and several sites (smaller than research bases) of AIST all over Japan. About 2300 researchers (about 2050 with tenure: about 80 from abroad) and a few thousands of visiting scientists, post-doctoral fellows, and students from home and abroad are working at AIST. About 650 permanent administrative personnel and many temporary staff support research works of AIST.
More information about AIST can be found at http://www.aist.go.jp/aist_e/about_aist/index.html

Contact:
Hanne Degans, External Communications Officer, T: +32 16 28 17 69, Mobile : +32 486 06 51 75, hanne.degans@imec.be



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