PhD

Process Technology

• Ge and III-V high mobility MOS devices for logic application
• Self aligned assembly for 3D silicon integration
• In-depth understanding of Cu/low-k reliability
• The effect of forces on the nano-scale on the functioning an
• Modelling study of the impact of mechanical shock, vibration
• Study of Avalanche Photodiodes based on Ge-on-Si technology
• Analog Circuit design for integrated optical-electrical inte
• High speed transceivers for photonic interconnects
• Implementation of Directed-Self Assembly for Advanced Lithog
• 2D Nanolattices for future nanoelectronic devices
• Ab-initio simulation of novel 2D materials
• Contacts to Ge and III-V
• Impact of interconnect multiple patterning options on circui
• Strength and reliability characterization of multi-level BEO
• Transient compact modeling methodologies for the thermal ana
• Probing of microscopic structures and structural defects by
• Thermal and electro-thermal characterization of GaN powerbar
• Surface preparation and cleaning of III-V materials
• Towards the control of nanoforces

Ge and III-V high mobility MOS devices for logic applications

Promoter: K. De Meyer
Supervisor: D. Lin
Program: Logic/GeIIIV

Description of topic

CMOS downscaling driven by Moore's law cannot be met anymore by simply reducing transistor dimensions since material properties such as the carrier mobility start to limit the device performance. The use of alternative materials that exhibit larger mobility such as III-V and Ge as the semiconductor in MOS structures may overcome such limitations. Recent developments on CMOS-driven III-V and Ge MOS (Metal-oxide-semiconductor) technologies provide new opportunities in advancing the performance envelope of logic devices as well as lowering the operating power.

Especially the combination of Ge pMOS devices with III-V nMOS to produce high speed CMOS circuits is a very tempting idea that could revolutionarize the microelectronics industry. However, many barriers still have to be overcome before this idea can be put into reality.

For n-MOS devices, III-V semiconductors, such as InGaAs or InP, emerge as promising replacements for Si due to their higher carrier mobility and lower bandgaps. For p-MOS application, GaSb could be a strong contender as an alternative to Si and Ge. The quest of high speed/low power post-Si CMOS with heterogeneous integration calls for in-depth studies on various aspects including device modeling and characterization, performance benchmarking, reliability/passivation/contact studies and ultimately, scaling beyond 22nm node.

The proposed research activities for the PhD program include (but not limited to):
1. Electrical characterization of III-V IFQW (Implant-free Quantum Well) MOS transistors for performance evaluation and device benchmark.
2. The passivation and reliability studies of high-k on III-V channels.
3. Scalability studies (EOT, channel length) on the IFQW MOS devices of 200mm/300mm p-line platform.
4. Fabrication of long-channel III-V MOS transistors.
5. Modeling and simulation of the IFQW (Implant-Free Quantum Well) MOS devices with different channel materials, gate stacks and layer structures.
6. Explore Vdd scaling to achieve low power operations.